Tetris for Altera DE2 FPGA

Wrote a Tetris game with Joohyun Lee for the Altera DE2.

Final project for ECE241 @ UToronto. (2nd year digital logic course with verilog). 2013 Fall semester.

2013-11-28 10.36.02

 

Code can be found below, will write a proper readme file around Christmas 2013.

Please don’t plagiarize!

Written with Quartus II 11.1 , service pack 2.11, Build 259 web edition

Controls:

A – move left

D – move right

W – change shape

Esc – Reset

(SW1 is a more powerful reset that resets the VGA adapter as well)

 

DE2 switch settings: All switches set to low EXCEPT SW3 (if keyboard does not work at all, try switching on SW17, keyboard generates debug output in LEDRs when working correctly with assigned keys)

 

Other keys with unimplemented features:

S – speeds up block falling; unimplemented feature.

Space – pause; unimplemented feature.

Enter – proceed;  unimplemented feature for loading screens and game over.

 

General unimplemented features:

Load game screen

Game over collision detection and game over screen

Rotation collision detection

Score counter and score update algorithms

Pausing

Game difficulty increasing

 

Known bugs:

Rotation will turn most blocks into a square block, and leave one block behind. This is most likely due to a bug with the block decoding module or it’s interface with the mainFSM.

Rows not being deleted past a certain height. Most likely caused by a counter overflow, or other arbitrary limit.

Blocks failing left of the screen. Should not happen without rotation, which is broken due to a lack of rotation detection.

Blocks appearing in middle(ish) of the screen if moved left/right when spawning. Caused by register “overflow” into “negative” numbers.

New block display not erasing the previous block properly. Caused by a bad line of code or 2 in the VGADATAPATH module.

Non-standard blocks not colliding. These debug blocks have discontinuities vertically or horizontally, which breaks the collision algorithm.

“Block Diagram”:

ECE241Project

 

Other scrap that I thought was important:

 

mainFSM_state_diagramrow_detection_logic

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